1. Field of the Invention
The present invention relates to a serial control apparatus and, more particularly, to a serial control apparatus for use in a video editing apparatus, VTR, video camera or the like.
2. Description of the Prior Art
Conventional video editing apparatus use a mother printed-circuit board on which a plurality of printed-circuit cards including a reference signal generator card, a mixer card, and an input circuit card are mounted, thus enhancing card mounting efficiency as a whole.
The cards mounted on the mother board are managed and controlled overall by a control central processing unit (hereinafter referred to as a CPU) mounted on the mother board and uses serial control signals. For instance, as shown in FIG. 3 of the accompanying drawings, the apparatus comprises a CPU 5 and a plurality of cards 3 (3A, 3B, . . . , 3N) interconnected with each other on a mother board 2 by a common bus 6 with the CPU 5 controlling the cards 3A, 3B, . . . 3N by its serial control signal.
Each of the cards 3A, 3B, . . . 3N may carry a single integrated circuit (hereinafter referred to as an IC); frequently, however, each card carries a plurality of ICs which provide either the same or different functions. Thus in the serial control, not only is a particular card controlled by a serial control signal but also each IC on the card is controlled by the same serial control signal. Consequently, such cards are often constituted as shown in FIG. 4 of the accompanying drawings.
The cards 3A, 3B, . . . 3N have the same basic constitution and differ only in the type or functionality of the ICs mounted on them. Therefore, the following description will be of only the card 3A as shown in FIG. 4 by way of example.
In an example shown in FIG. 4, a number "M" of ICs, IC11A through 11M are mounted on the card 3A. A serial interface 12 is attached to the card 3A to control these ICs. The serial interface 12 comprises a serial-parallel converter 14 for converting an address data ADD and its address decoder 15. The address decoder 15 generates chip select signals CS1, CS2, . . . CSm corresponding to IC11A, 11B, . . . 11M for selecting particular ICs.
The address decoder 15 also controls supply of data WDATA to be written to a single or plurality of registers, not shown, installed on the IC11A, 11B, . . . 11M and write and read control signals to a data controller 13 for controlling a data RDATA read from the registers.
When the card 3A is mounted on the mother board 2, a connector 18 of the card is coupled with a connector 19 of the mother board. The connector 19 has a connection pattern unique to that card. In this example, five connector pins are connected to a power or ground line according to the connection pattern. When the connectors are mated, an identification code (slot address) SLOTADD corresponding to each card number (slot number) is generated. The slot address SLOTADD is fed to the address decoder 15.
The mother board 2 and the card 3A are connected through the common bus 6 FIG. 3. Reference numerals 17a through 17d in the accompanying drawings indicate input pins on the card 3A. When an address data ADD synchronized with a clock signal CK (shown in FIG. 5 as B and A respectively) comes from the mother board 2 to the card 3A, this serial address data is converted by the serial-parallel converter 14 to an equivalent parallel data to be fed to the address decoder 15.
At the address decoder 15, slot address ADS consisting of first 5 bits of the address data ADD is compared with the slot address SLOTADD on the card 3A. If they are found matching, it is determined that the card 3A has been selected and the address data ADD that follows the slot address ADS is interpreted.
In interpreting the input address data ADD, error detection is performed on the address data ADD based on parity sign P attached to an end thereof. If no error has been detected or when error correction has been completed, an IC specified by an IC address data ICAD is accessed. Access to the IC is made by a chip select signal CSi (i=1 to m). Because the chip select signal or signals CSi are all generated by the address decoder 15, m chip select signal lines are provided, m corresponding to the number of ICs mounted on the card.
When the IC has been selected, data is written to a single or a plurality of registers, not shown, provided on the IC. The data is written to an area specified by a register address REGAD. During data read, a register or an IC is specified and contents of the specified register or IC are read out.
When the card is composed as shown in FIG. 4, the number of chip select signal lines from the address decoder 15 increases in proportion to the number of ICs mounted on the card because the ICs are selectively specified by the address decoder 15. As a result, when the number of mounted ICs increases, the scale of the card carrying the ICs will increase accordingly.